1. Field of the Invention
The present invention relates generally to methods for fabricating semiconductor devices and, more particularly, to methods for reducing cell pitch in semiconductor devices.
2. Description of Related Art
The fabrication of semiconductor devices is a complex process, which typically includes a number of photolithography processes. In a typical photolithography process, a photoresist material is deposited over a layer to be patterned and is exposed to a radiation source, such as, for example, ultraviolet radiation, which is projected through a mask that defines the pattern to be formed in the photoresist. The mask only passes radiation to selected regions of the layer to be patterned, resulting in the exposure of the photoresist only at those selected regions. The photoresist is then developed to form a patterned photoresist layer over the underlying layer to be patterned. The portions of the underlying layer left exposed by the photoresist are etched away to define, for example, gate conductors of ensuing transistor devices. The pattern in the photoresist is thus replicated in the underlying layer.
Important advantages are of course achieved by making the semiconductor devices as small as possible. Typical photolithography processes, however, limit the size and density with which semiconductor devices may be fabricated. For example, a minimum resolution capability of a given photolithography process determines the minimum pitch with which features for a patterned layer may be printed using that process. Consequently, the photolithography process limits the minimum achievable widths which can be obtained for those features of such conventional semiconductor devices. It therefore can be difficult to reduce the widths of and distances between, for example, transistor gate conductors that are defined by the photolithography process.
Because of limitations of the photolithography process, the pitch of semiconductor devices, such as for example transistor devices, cannot be easily reduced. The “pitch” is herein defined as the distance between the same points of two adjacent structures of the same type, such as, for example, two adjacent transistor gate conductors. Since the pitch of semiconductor devices cannot be easily reduced, the device density cannot easily be increased to meet the high demand for smaller and faster semiconductor devices. In addition, higher densities translate into lower material costs for the semiconductor devices.
A need thus exists in the prior art to reliably and efficiently reduce the pitch of semiconductor devices. A further need exists to develop methods for fabricating semiconductor devices in which the widths of and distances between adjacent structures of the same type are not limited by the photolithography process.